1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a delay test circuit measuring signal delay generated in an internal circuit of the semiconductor device.
2. Description of Related Art
In recent years, there has been a problem in a semiconductor device that signal delay is occurred in the semiconductor device along with miniaturization of a manufacturing process and this signal delay causes malfunction. In order to measure this signal delay, a delay test circuit is often embedded in the semiconductor so as to measure the signal delay in the semiconductor device.
The signal delay is also occurred in an output of the semiconductor device. The signal delay in the output is occurred by resistance component or capacitance component that is parasitic in line connected to an external output terminal. Further, in the semiconductor device that is manufactured by using the miniaturized semiconductor process, an internal circuit is formed by element having low breakdown voltage and small size. It is therefore possible in the internal circuit to reduce chip size and power consumption due to low power supply voltage. On the other hand, the output is formed by element having higher breakdown voltage and larger size than the internal circuit. Then it is possible for the output to operate by power supply voltage that is higher than that of the internal circuit and to output signal having larger amplitude to the line connected to the external output terminal.
If the delay test circuit is formed adjacent to the output in such a semiconductor device so as to measure the signal delay that is occurred in the output, the circuit size in the output is increased, which means the chip size is increased. In order to overcome this problem, in the conventional example, the signal delay of the output is measured by outputting signals from the internal circuit to the output, connecting dummy capacitor predicting parasitic capacitance that is parasitic in the connected line with the external output terminal, and monitoring the signal that is delayed by the dummy capacitor. The example of such measurement system is disclosed in Japanese Unexamined Patent Application Publication No. 2005-78547 (patent document 1).
In this conventional example, the capacitor simulated as a line capacitor is connected to the external output terminal (terminal that is to be measured). Then signal output from the output buffer through the external output terminal and whose rising is delayed by the capacitor is input through the input buffer connected to the external output terminal. Then the signal delay at the output is measured by measuring timing where the signal is input to the output buffer and timing where the signal is input from the input buffer at the delay time measuring circuit. (See 0052-0059 and FIGS. 11 to 13 in patent document 1).
However, the signal delay occurred in the circuit of the output buffer is quite small compared with the signal delay occurred in the line capacitor. Therefore, if the signal delay is measured in the system including the line capacitor as in the conventional example, the delay amount due to the circuit of the output buffer may be confused with the whole delay amount. Therefore, in the conventional example, the delay occurred in the circuit of the output buffer cannot be measured with accuracy.